This invention relates to a process for etching semiconductor devices, and more particularly to a process for effectively and efficiently isotropically etching multi-layer semiconductor devices having adjacent tungsten silicide-polysilicon layers.
It is known in the prior art that the manufacture of multi-layer semiconductor devices typically involves patterned etching of areas of the semiconductor surface which is not covered by a pattern of photoresist protective material. These etching techniques use liquid or wet etching materials, or dry etching with halogens or halogen-containing compounds, of certain layers of these devices. For example, one well known etching material is a chlorine-containing plasma where chlorine gas, hydrogen chloride or other feed gas may be the source of the chlorine. Chlorine etches the semiconductor isotropically, i.e., in both a lateral and vertical direction. This results in an etched feature which has a line width which is smaller than the exposed resist image.
Etching of the semiconductor devices can be conducted in a gas phase using known techniques such as plasma etching, ion beam etching, and reactive ion etching. In isotropic plasma etching the requisite portion of the surface to be etched is removed by a chemical reaction between gaseous ions, radicals, or reactive chemicals from the ionized feed and the subject surface. In the anisotropic process, etching takes place only or primarily in the vertical direction so that feature widths substantially match the photoresist pattern widths. For example, in U.S. Pat. No. 4,734,157 an elemental silicon-containing layer, such as a layer of polysilicon or silicide, is etched anisotropically employing a gas plasma comprising a gaseous chlorofluorocarbon, capable of supplying CF.sub.x and chlorine ions, and ammonia. Profile control of a silicon layer is controlled by the use of this etching mode.
A problem which occurs during the isotropic plasma etching of multilayer semiconductor materials is matching the horizontal etch rates of the dissimilar materials which make up the semiconductor structure. For example, as shown in FIG. 1, the metal layers of semiconductor device 10A are adjacent tungsten silicide 12-polysilicon 14 layers on a layer of silicon dioxide 18 which is under a photoresist layer 16. This structure is used in the formation of, for example, an L.D.D. MOS transistor. When a chlorine plasma or SF6 plasma etchant is employed, an over etch situation can occur in which the polysilicon layer 14 is undercut much faster than the tungsten silicide layer 12 leaving a blocking ledge. This ledge will subsequently block the lightly doped drain implant process and prevent formation of source and drain regions of the transistor or the underlapping edge of the gate region. It can also serve as a topology and void problem at later fabrication stages.
In another etching sequence involving SF6/O2, the tungsten silicide layer 12 will undercut too fast under photoresist layer 16 resulting in an undesirable over etch of the silicide layer 14 so that semiconductor device 10B has a configuration similar to that shown in FIG. 2. In this case, an asymmetrical profile having high resistance runners are formed in which the tungsten silicide layer 12 is significantly narrower than the polysilicon layer 14. This produces a high resistant electrical connector which is an undesirable property in commercial use.
When SF6/O2/CI2 plasma is used to solve the uneven undercutting problem by matching the profiles of the respective tungsten silicide and polysilicon layers, the resist sidewalls are chemically attacked by oxygen gas causing the fabricator to use much larger sized resist starting geometries in order to compensate for the above erosion conditions. The use of such larger resist layers adversely effects the spacing density of the etched devices along the silicon support and substantially adds to the cost of manufacture of the semiconductor device.
Therefore, a need exists for an isotropic semiconductor etching process which forms the requisite resist-tungsten silicide-polysilicon configuration required for effective formation of L.D.D. MOS transistors during the source drain ion implantation process with minimum resist loss and with correspondingly reduced usage of resist material.